Compact Hardware Implementation Of The CLEFIA Block Cipher

Abstract

This study presents the implementation of the CLEFIA block cipher, a lightweight symmetric encryption algorithm, with a focus on its application in secure communication and data protection. In recent years, several lightweight block ciphers for hardware implementation have been proposed. Block ciphers are used to protect data in cryptographic applications. CLEFIA is known for its strong security properties and efficient performance, making it suitable for resource-constrained environments. The objective of this report is to implement CLEFIA algorithm in hardware description language and to develop a hardware implementation of the CLEFIA algorithm with less memory space requirement. The report provides an overview of the CLEFIA algorithm, including its round structure, key expansion, and encryption/decryption processes. The implementation process utilizes Verilog, a hardware description language, to design the 128-bit key length of CLEFIA hardware modules. The VCS simulation tool is employed for functional verification, ensuring the correctness of the implementation. Additionally, Design Compiler, a synthesis tool, is utilized for optimizing the design and generating efficient gate-level representations. By incorporating modern tools like VCS, and Design Compiler, along with a modular design technique, the report presents a practical and efficient approach to implementing 128-bit key length of CLEFIA. The use of concurrency and optimized circuitry to carry out high-speed encryption operations is highlighted in the discussion of 128-bit key length of CLEFIA's implementation in hardware. This report outcome has successfully achieved the implementation of 128-bit key length of CLEFIA and successfully reduce the Gate Equivalence (GE) by 76.07% after replacing (96x32)-bit Memory block with Constant Generator and Round Key Generator. This report also examines the possible advantages of CLEFIA implementation in hardware, including improved performance, resource efficiency, and effortless integration with current systems and protocols.