Symmetrical Unit-Cell Numerical Approach for Flip-Chip Underfill Flow Simulation
Keywords:bump pitch, electronic packaging, finite volume method (FVM), flip-chip, underfill encapsulation
Underfill process is a critical manufacturing process to safeguard and enhance the package reliability of flip-chip devices. In most underfill researches, the underfill flow was primarily investigated through numerical simulation. Nonetheless, the numerical simulation required a tremendously long time to complete. This paper presents a new symmetrical unit-cell approach to simulate the flip-chip underfill encapsulation process. The current numerical simulation is based on the finite volume method scheme. By exploiting the repetitive symmetry of bump array in flip-chip, the computational domain was simplified into a long array of unit-cells of one-pitch thick while the symmetrical walls between adjacent unit-cells were modelled using the periodic boundary condition. Accordingly, the computational costs can be greatly reduced. Alongside with the introduction of a new numerical approach of flip-chip underfill, the variation effect of bump pitch was studied by considering four flip-chip cases with bump pitches ranging from 0.08 mm to 0.16 mm. The numerical findings were found to in great consensus to the referencing experimental data, with the discrepancy, not more than 14.54%. Additional validation with the analytical filling time model revealed that both the numerical and analytical filling progressions are comparable. It is found that the increases in bump pitch can reduce the filling time at a particular filling distance, such that the filling time was halved within the investigated range of bump pitch. This new numerical approach is particularly useful for the simulation works of underfill process, especially the design and process optimization.