Design of Optimized Pipelined RIPEMD-160 with High Frequency and Throughput

Abstract

The main objective of this paper is to design optimized pipelined RIPEMD-160 with efficient design strategies. There are two proposed designs in this paper such as iterative design and pipelined design. The results show the pipelined design provides high frequency as well as throughput of the design. The improvement of these designs based on HDL design style where the placement of register need to be considered, by adding the several register to the design and by using Quartus II Advisor tools. Furthermore, by using TimeQuest Timing Analyzer, timing requirement of the design such as setup and hold time of the design can be achieved and the maximum frequency of the design can be obtained. This paper focuses on maximum frequency of the designs. Therefore, the methodology on how to improve the speed of the design needs to be taken into consideration. In addition, nowadays high throughput of the hash function design is important since all the design need to be fast enough through some application. By using pipelined design, the frequency and throughput of the design can be improved which is about 250 MHz and 7.805 Gbps respectively with small area implementation.