Low Power 7 nm FinFET based 6T-SRAM Design

Hanady  H. Issa; Mahmoud S.  Badran; Saleh M.  Eisa; Hani F.  Ragai

Low Power 7 nm FinFET based 6T-SRAM Design

Authors

Hanady H. Issa Dept. of Electronics and Communications, Arab Academy for Science and Technology, Cairo, Egypt
Mahmoud S. Badran Dept. of Electronics and Communications, Arab Academy for Science and Technology, Cairo, Egypt
Saleh M. Eisa Dept. of Electronics and Communications, Arab Academy for Science and Technology, Cairo, Egypt
Hani F. Ragai Dept. of Electronics and Communications, Ain Shams University, Cairo, Egypt

Keywords:

7nm Bulk FinFET, 6T-SRAM, BSIM-CMG, RSNM, WLWM, standby power

Abstract

FinFET based SRAM design makes the SRAM more appealing in the low power applications. This paper presents a 7 nm FinFET device characterization utilizing the compact model BSIM-CMG. In addition, the paper provides simulations for different stability parameters, access time, and standby power of two 6T-SRAM cells designs consisting of different fin count. The standby power for both cells are 149 and 198 pW/µm with better read stability for the later design while the access time is constant for both cells (30 ps). The read/write operation of the two SRAM cells is stable with reducing the power supply to 0.5 V.

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Published

2020-11-01

How to Cite

H. Issa, . H. ., Badran, M. S. ., Eisa, . S. M., & Ragai, . H. F. . (2020). Low Power 7 nm FinFET based 6T-SRAM Design . Journal of Advanced Research in Applied Mechanics, 42(1), 12–17. Retrieved from https://akademiabaru.com/submit/index.php/aram/article/view/1808